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fujitsu microelectronics data sheet copyright?2008-2009 fujitsu microelect ronics limited all rights reserved 2009.1 for the information for microcontroller supports, see the following web site. http://edevice.fujitsu.com/micom/en-support/ 16-bit microcontroller cmos f 2 mc-16lx mb90820b series mb90822b/823b/f822b/f823b/f828b/v820b description the mb90820b series is a line of general-purpose, fujitsu 16-bit microcontrollers designed for process control applications which require high-speed real-t ime processing, such as consumer products. while inheriting the at architecture of the f 2 mc family, the instruction set for the f 2 mc-16lx cpu core of the mb90820b series incorporates additional instructions for high-level languages, supports extended addressing modes, and contains enhanced multiplication and division instructions as well as a substantial collection of improved bit manipulation instructions. in addition, the mb90820b series has an on-chip 32-bit accumulator which enables processing of long-word data. the peripheral resources integrated in the mb90820b series include : an 8/10-bit a/d converter, 8-bit d/a con- verters, uarts (sci) 0, 1, multi-functional timer (16-bit free-run timer, input capture units (icus) 0 to 3, output compare units (ocus) 0 to 5, 16-bit ppg timer 0, waveform generator), 16-bit ppg timer 1, 2, pwc 0, 1, 16-bit reload timer 0, 1 and dtp/external interrupt. note : f 2 mc is the abbreviation of fujitsu flexible microcontroller. features ? minimum execution time of instruction : 42 ns / 4 mhz oscillation (uses pll clock multiplication) maximum multiplier = 6 maximum memory space 16 m bytes, linear/bank access instruction set optimized for controller applications supported data types : bit, byte, word, and long-word types standard addressing modes : 23 types 32-bit accumulator enhancing high-precision operations signed multiplication/divi sion instructions and enhanced reti instructions (continued) ds07-13751-2e www.datasheet.in
mb90820b series 2 ds07-13751-2e (continued) enhanced high level language (c) and multi-tasking support instructions use of a system stack pointer symmetrical instruction set and barrel shift instructions program patch function (for two address pointers) increased execution speed : 4-byte instruction queue powerful interrupt function up to eight priority levels programmable external interrupt inputs : 8 channels automatic data transmission function independent of cpu operation up to 16 channels for the extended intelligent i/o service dtp request inputs : 8 channels internal rom flash memory : 64 k/128 k bytes with flash security mask rom : 64 k/128 k bytes internal ram evaluation product : 16 k bytes flash memory : 4 k/8 k bytes mask rom : 4 k bytes general-purpose ports up to 66 channels (ports where pull-up resistor can be configured : 32 channels) a/d converter (rc) : 16 channels 8/10-bit resolution selectable conversion time : min 3 s (24 mhz operation, including sampling time) 8-bit d/a converter : 2 channels uart : 2 channels 16-bit ppg timer : 3 channels mode switching function provided (pwm mode or one-shot mode) ch.0 can be worked with multi-functional timer or independently 16-bit reload timer : 2 channels 16-bit pwc timer : 2 channels clock supervisor multi-functional timer input capture : 4 channels output compare with selectable buffer : 6 channels free-run timer with up or up-down mode selection and selectable buffer: 1 channel 16-bit ppg timer : 1 channel waveform generator : (16-bit timer : 3 channels, 3-phase waveform or dead time) time-base timer/watchdog timer : 18-bit low-power consumption mode : sleep mode stop mode cpu intermittent operation mode package : lqfp-80 (fpt-80p-m21 : 0.50 mm pitch) lqfp-80 (fpt-80p-m22 : 0.65 mm pitch) qfp-80 (fpt-80p-m06 : 0.80 mm pitch) cmos technology www.datasheet.in
mb90820b series ds07-13751-2e 3 product lineup (continued) part number item mb90v820b mb90f822b MB90F823B mb90f828b mb90822b mb90823b classification evaluation product flash memory product with flash security mask rom product rom size ? 64 k bytes 128 k bytes 128 k bytes 64 k bytes 128 k bytes ram size 16 k bytes 4 k bytes 8 k bytes 4 k bytes cpu function number of instruction : 351 minimum execution time : 42 ns / 4 mhz (pll 6) addressing mode : 23 data bit length : 1, 8, 16 bits maximum memory space: 16 m bytes i/o port i/o port (cmos) : 66 pwc pulse width counter timer : 2 channels timer function (select the counter timer from three internal clocks) various pulse width measuring function (?h? pulse width, ?l? pulse width, rising edge to fall- ing edge period, falling edge to rising edge period, rising edge to rising edge period and fall- ing edge to falling edge period) uart uart : 2 channels with full-duplex double buffer (8-bit length) clock asynchronized or clock synchronized tr ansmission (with start and stop bits) can be selected and used. transmission can be one-to-one (bidirectional communication) or one-to-n (master-slave communication). 16-bit reload timer reload timer : 2 channels reload mode, single-shot mode or event count mode selectable 16-bit ppg timer ppg timer : 3 channels pwm mode or single-shot mode selectable ch.0 can be worked with multi-functional timer or independently. multi-functional timer (for ac/dc motor control) 16-bit free-run timer with up or up-down mode selection and buffer : 1 channel 16-bit output compare : 6 channels 16-bit input capture : 4 channels 16-bit ppg timer : 1 channel waveform generator (16-bit timer : 3 channels, 3-phase waveform or dead time) 8/10-bit a/d converter 8/10-bit resolution (16 channels) conversion time : min 3 s (24 mhz internal clock, including sampling time) 8-bit d/a converter 8-bit resolution (2 channels) dtp/external interrupt 8 independent channels interrupt trigger : rising edge, falling edge, ?l? level or ?h? level clock supervisor no yes no low-power consumption stop mode / sleep mode / cpu intermittent operation mode www.datasheet.in
mb90820b series 4 ds07-13751-2e (continued) *1 : mb90v820b is operating guaranteed temperature 0 c to + 25 c. *2 : configured by a jumper switch (tool vcc) when emulator (mb2147-01) is used. please refer to the mb2147-01 or mb2147-20 hardware manual (3.3 emulator-dedicated power supply switching) about details. package and corres ponding products : available x : not available note: for more information about each package, refer to ? package dimensions?. part number item mb90v820b mb90f822b MB90F823B mb90f828b mb90822b mb90823b package pga-299 lqfp-80 (fpt-80p-m21 : 0.50 mm pitch) lqfp-80 (fpt-80p-m22 : 0.65 mm pitch) qfp-80 (fpt-80p-m06 : 0.80 mm pitch) power supply voltage for operation 4.5 v to 5.5 v* 1 3.5 v to 5.5 v : normal operation when a/d converter and d/a converter are not used 4.0 v to 5.5 v : normal operation when d/a converter is not used 4.5 v to 5.5 v : normal operation when a/d converter and d/a converter are used process cmos emulator power supply* 2 included ? package mb90v820b mb90f822b MB90F823B mb90f828b mb90822b mb90823b pga-299 x x x x x fpt-80p-m21 x fpt-80p-m22 x fpt-80p-m06 x www.datasheet.in
mb90820b series ds07-13751-2e 5 differences among products memory size in evaluation with an evaluation product, note the diff erence between the evaluation product and the product actually used. the following items must be taken into consideration. the mb90v820b does not have an internal rom, however, operations equivalent to chips with an internal rom can be evaluated by using a dedicated development tool, enabling selection of rom size by settings of the development tool. in the mb90v820b, images from ff8000 h to ffffff h are mapped to bank 00, and fe0000 h to ff7fff h are mapped to bank fe and bank ff only. (this setting can be changed by configuring the development tool.) in the mb90822b/f822b/f828b, images from ff8000 h to ffffff h are mapped to bank 00, and ff0000 h to ff7fff h are mapped to bank ff only. in the mb90823b/f823b/f828b, images from ff8000 h to ffffff h are mapped to bank 00, and fe0000 h to ff7fff h are mapped to bank fe and bank ff only. clock supervisor function the clock supervisor is built-in in mb90f828b only. note t hat the evaluation products and products actually used are different when evaluating evaluation products. please contact the sales representatives for more information on evaluation of this function. modify rom data the registers include this function between 001ff0 h and 001ff5 h which overlap the ram area of mb90f828b. do not access to the ram when using this function in mb90f282b. www.datasheet.in
mb90820b series 6 ds07-13751-2e pin assignment (continued) * : high current pin. avr avcc avss p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 p51/int7 p50/ppg2 p47/pwo1 p46/pwi1 p45/sin0 p44/sot0 p43/sck0 rst p42/to0 p41/tin0 vss x0 x1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 md0 md1 md2 p40/ppg1 p37/ppg0 p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 c vss vcc p00 * p01 * p02 * p03 * p04 * p05 * p06/pwi0 * p07/pwo0 * p10/int0/dtti p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17 p20/tin1 p21/to1 p22 vcc p23 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p70/da0/an8 p71/da1/an9 p72/sin1/an10 p73/sot1/an11 p74/sck1/an12 p75/frck/an13 p76/in0/an14 p77/in1/an15 p80/in2 p81/in3 p82/rto0(u) * p83/rto1(x) * p84/rto2(v) * p85/rto3(y) * p86/rto4(w) * p87/rto5(z) * 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 (top view) (fpt-80p-m06) qfp-80 www.datasheet.in
mb90820b series ds07-13751-2e 7 (continued) * : high current pin. avss p67/an7 p66/an6 p65/an5 p64/an4 p63/an3 p62/an2 p61/an1 p60/an0 p51/int7 p50/ppg2 p47/pwo1 p46/pwi1 p45/sin0 p44/sot0 p43/sck0 rst p42/to0 p41/tin0 vss 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 x0 x1 md0 md1 md2 p40/ppg1 p37/ppg0 p36 p35 p34 p33 p32 p31 p30 p27 p26 p25 p24 p23 vcc 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 vcc p00 * p01 * p02 * p03 * p04 * p05 * p06/pwi0 * p07/pwo0 * p10/int0/dtti p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17 p20/tin1 p21/to1 p22 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 avcc avr p70/da0/an8 p71/da1/an9 p72/sin1/an10 p73/sot1/an11 p74/sck1/an12 p75/frck/an13 p76/in0/an14 p77/in1/an15 p80/in2 p81/in3 p82/rto0(u) * p83/rto1(x) * p84/rto2(v) * p85/rto3(y) * p86/rto4(w) * p87/rto5(z) * c vss 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 (top view) (fpt-80p-m22) (fpt-80p-m21) lqfp-80 www.datasheet.in
mb90820b series 8 ds07-13751-2e pin description (continued) pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 21, 22 23, 24 x0,x1 a oscillating oscillation pins. 17 19 rst b reset input external reset input pin. 59 to 54 61 to 56 p00 to p05 c port input general-purpose i/o ports. 53 55 p06 c general-purpose i/o port. pwi0 pwc ch.0 signal input pin. 52 54 p07 c general-purpose i/o port. pwo0 pwc ch.0 signal output pin. 51 53 p10 d general-purpose i/o port. int0 external interrupt request input ch.0 pin. dtti rto0 to rto5 pins for fixed-level input. this func- tion is enabled when the waveform generator spec- ifies its input bits. 50 to 45 52 to 47 p11 to p16 d general-purpose i/o ports. int1 to int6 external interrupt request input ch.1 to ch.6 pins. 44 46 p17 d general-purpose i/o port. 43 45 p20 d general-purpose i/o port. tin1 external clock input pin for reload timer ch.1. 42 44 p21 d general-purpose i/o port. to1 event output pin for reload timer ch.1. 41, 39 to 35 43, 41 to 37 p22 to p27 d general-purpose i/o ports. 34 to 28 36 to 30 p30 to p36 e general-purpose i/o ports. 27 29 p37 e general-purpose i/o port. ppg0 output pin for ppg timer ch.0. 26 28 p40 f general-purpose i/o port. ppg1 output pin for ppg timer ch.1. 19 21 p41 f general-purpose i/o port. tin0 external clock input pin for reload timer ch.0. 18 20 p42 f general-purpose i/o port. to0 event output pin for reload timer ch.0. www.datasheet.in
mb90820b series ds07-13751-2e 9 (continued) pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 16 18 p43 f port input general-purpose i/o port. sck0 serial clock i/o pin for uart ch.0. 15 17 p44 f general-purpose i/o port. sot0 serial data output pin for uart ch.0. 14 16 p45 g general-purpose i/o port. sin0 serial data input pin for uart ch.0. 13 15 p46 f general-purpose i/o port. pwi1 pwc ch.1 signal input pin. 12 14 p47 f general-purpose i/o port. pwo1 pwc ch.1 signal output pin. 11 13 p50 f general-purpose i/o port. ppg2 output pin for ppg timer ch.2. 10 12 p51 f general-purpose i/o port. int7 external interrupt request input ch.7 pin. 9 to 2 11 to 4 p60 to p67 h analog input general-purpose i/o ports. an0 to an7 a/d converter analog input pins. 78, 77 80, 79 p70, p71 i general-purpose i/o ports. da0, da1 d/a converter analog output pins. an8, an9 a/d converter analog input pins. 76 78 p72 j general-purpose i/o port. sin1 serial data input pin for uart ch.1. an10 a/d converter analog input pin. 75 77 p73 k general-purpose i/o port. sot1 serial data output pin for uart ch.1. an11 a/d converter analog input pin. 74 76 p74 k general-purpose i/o port. sck1 serial clock i/o pin for uart ch.1. an12 a/d converter analog input pin. 73 75 p75 k general-purpose i/o port. frck external clock input pin for free-run timer. an13 a/d converter analog input pin. www.datasheet.in
mb90820b series 10 ds07-13751-2e (continued) *1 : fpt-80p-m21, fpt-80p-m22 *2 : fpt-80p-m06 *3 : refer to ? i/o circuit type? for details on the i/o circuit types. pin no. pin name i/o circuit * 3 pin status during reset function lqfp * 1 qfp * 2 72, 71 74, 73 p76, p77 k analog input general-purpose i/o ports. in0, in1 trigger input pins for input capture ch.0, ch.1. an14, an15 a/d converter analog input pins. 70, 69 72, 71 p80, p81 f port input general-purpose i/o ports. in2, in3 trigger input pins for input capture ch.2, ch.3. 68 to 63 70 to 65 p82 to p87 l general-purpose i/o ports. rto0 (u) to rto5 (z) waveform generator output pins. (u) to (z) represent the coils for contro lling a 3-phase motor. 25 27 md2 m mode input input pin for operation mode specification. 24, 23 26, 25 md1, md0 n input pins for operation mode specification. 80 2 av cc ? ? analog power supply pin. 79 1 avr ? vref + pin for the a/d converter. vref - is fixed to avss internally. 13av ss ? analog power supply (ground) pin. 20, 61 22, 63 vss ? power (ground) pins. 40, 60 42, 62 vcc ? power pins. 62 64 c ? connect pin for smoothing capacitor to stabilize internal power supply. www.datasheet.in
mb90820b series ds07-13751-2e 11 i/o circuit type (continued) classification type remarks a oscillation feedback resistor : approx. 1 m ? b hysteresis input pull-up resistor : approx. 50 k ? c cmos output hysteresis input selectable pull-up resistor : approx. 50 k ? i ol = 12 ma d cmos output hysteresis input selectable pull-up resistor : approx. 50 k ? i ol = 4 ma e cmos output cmos input with pull-up control i ol = 4 ma x1 x0 p-ch n-ch clock input standby control signal r p-ch n-ch r p-ch digital output pull-up control hysteresis input digital output standby mode control p-ch n-ch r p-ch digital output pull-up control hysteresis input digital output standby mode control p-ch n-ch r p-ch digital output pull-up control cmos input digital output standby mode control www.datasheet.in
mb90820b series 12 ds07-13751-2e (continued) classification type remarks f cmos output hysteresis input i ol = 4 ma g cmos output hysteresis input cmos input (selectable for uart ch.0 data input pin) i ol = 4 ma hcmos output cmos input analog input i ol = 4 ma i cmos output hysteresis input analog output analog input i ol = 4 ma p-ch n-ch digital output hysteresis input digital output standby mode control p-ch n-ch digital output hysteresis input digital output standby mode control cmos input p-ch n-ch cmos input analog input control analog input digital output digital output p-ch n-ch digital output hysteresis input digital output analog i/o control analog output analog input www.datasheet.in
mb90820b series ds07-13751-2e 13 (continued) classification type remarks j cmos output hysteresis input cmos input (selectable for uart ch.1 data input pin) i ol = 4 ma kcmos output hysteresis input analog input i ol = 4 ma l cmos output hysteresis input i ol = 12 ma m mask rom / evaluation product hysteresis input pull-down resistor : approx. 50 k ? flash memory product cmos input no pull-down resistor n mask rom / evaluation product hysteresis input flash memory product cmos input p-ch n-ch digital output hysteresis input digital output analog input control cmos input analog input p-ch n-ch digital output hysteresis input digital output analog input control analog input p-ch n-ch digital output hysteresis input digital output standby mode control r www.datasheet.in
mb90820b series 14 ds07-13751-2e handling devices special care is required for the following when handling the device : preventing latch-up stabilization of supply voltage treatment of unused pins using external clock power supply pins (v cc /v ss ) pull-up/pull-down resistors crystal oscillator circuit turning-on sequence of power supply to a/d converter and analog inputs connection of unused pins of a/d converter notes on turning the power on notes on during operation of pll clock mode 1. preventing latch-up cmos ic chips may suffer latch-up under the following conditions : a voltage higher than v cc or lower than v ss is applied to an input or output pin. a voltage higher than the rated voltage is applied between v cc and v ss pins. the av cc power supply is applied before the v cc voltage. latch-up may increase the power supply current drastically, causing thermal damage to the device. in using the devices, take sufficient care to avoid exceeding maximum ratings. for the same reason, also be careful not to let the analog power-supply voltage (av cc , avr) exceed the digital power-supply voltage. 2. stabilization of supply voltage a sudden change in the supply voltage may cause the device to malfunction even within the specified v cc supply voltage operation range. therefore, the v cc supply voltage should be stabilized. for reference, the supply voltage should be controlled so that v cc ripple variations (peak-to-peak values) at commercial frequencies (50 hz/60 hz) fall below 10 % of the standard v cc supply voltage and the coefficient of fluctuation does not exceed 0.1 v/ms at instantaneous power switching. 3. treatment of unused pins leaving unused input pins open may result in misbehavior or latch up and possible permanent damage of the device. therefore they must be pulled up or pulled down through resistors. in this case those resistors should be more than 2 k ? . unused bidirectional pins should be set to the output state and can be left open, or the input state with the above described connection. 4. using external clock to use external clock, drive the x0 pin and leave x1 pin open. x0 x1 mb90820b series open www.datasheet.in
mb90820b series ds07-13751-2e 15 5. power supply pins (v cc /v ss ) if there are multiple v cc and v ss pins, from the point of view of device design, pins to be of the same potential are connected the inside of the device to prevent such malfunctioning as latch up. to reduce unnecessary radiation, prevent malfunctioning of the strobe signal due to the rise of ground level, and observe the standard for total output current, be sure to connect the v cc and v ss pins to the power supply and ground externally. connect v cc and v ss pins to the device from the current supply source at a low impedance. as a measure against power supply noise, connect a capacitor of about 0.1 f as a bypass capacitor between v cc and v ss pins in the vicinity of v cc and v ss pins of the device. 6. pull-up/pull-down resistors the mb90820b series does not support internal pull-up/pull-down resistors option (port 0 to port 3 : built-in pull- up resistors) . use external components where needed. 7. crystal oscillator circuit noises around x0 or x1 pins may be possible causes of abnormal operations. make sure to provide bypass capacitors via shortest distance from x0, x1 pins, crystal oscillator (or ce ramic oscillator) and ground lines, and make sure, to the utmost effort, that lines of oscillation circuit do not cros s the lines of other circuits while you design a printed circuit board. it is highly recommended to provide a printed circuit boa rd art work surrounding x0 and x1 pins with a ground area for stabilizing the operation. 8. turning-on sequence of power supply to a/d converter and d/a converter, and analog inputs make sure to turn on the a/d converter po wer supply, d/a converter power supply (av cc , avrh, avr) and analog inputs (an0 to an15) after turning-on the digital power supply (v cc ). turn-off the digital power after turning off the a/d converter power supply, d/a converter power supply, and analog inputs. in this case, make sure that the voltage not exceed avr or av cc (turning on/off the analog and digital power supplies simultaneously is acceptable). 9. pin connections when a/d converter and d/a converter are unused when the a/d converter and d/a converter are not used, connect av cc = v cc , av ss = avrh = avrl = v ss . v cc v cc v cc v cc v cc v ss v ss v ss v ss v ss mb90820b series www.datasheet.in
mb90820b series 16 ds07-13751-2e 10. notes on turning the power on to prevent the internal regulator circuit from malfunctioning, set the voltage rise time during power on at 50 s or more (0.2 v to 2.7 v) . 11. notes on during operation of pll clock mode if the pll clock mode is selected, the microcontroller may continue to operate at the free-running frequency of the self-oscillating circuit within the pl l even if the external oscillator is disconnected or external clock input is stopped. performance of this operation, however, cannot be guaranteed. 12. internal cr oscillation circuit parameter symbol rating unit min typ max oscillation frequency f rc 50 100 200 khz oscillation stabilization waiting time tstab ?? 100 s www.datasheet.in
mb90820b series ds07-13751-2e 17 sector configurat ion of flash memory the flash memory has the sector conf iguration illustrated below. the addresses in the illustration are the upper and lower addresses of each sector. when 512k bits flash memory is accessed from the cpu, sa0 to sa3 are allocated in the ff bank. when 1024k bits flash memory is accessed from the cpu, sa0 to sa4 are allocated in the fe and ff bank. * : the writer address is the address corresponding to the cpu address when writing data from a parallel flash memory writer. use the writer address when programming or erasing using a general-purpose parallel writer. sa3 (16k bytes) sa2 (8k bytes) sa1 (8k bytes) sa0 (32k bytes) flash memory cpu address *writer address ffffff h 7ffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fff h ff0000 h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h sa4 (16k bytes) sa3 (8k bytes) sa2 (8k bytes) sa1 (32k bytes) flash memory cpu address *writer address ffffff h 7ffff h ffc000 h ffbfff h ffa000 h ff9fff h ff8000 h ff7fff h ff0000 h 7c000 h 7bfff h 7a000 h 79fff h 78000 h 77fff h 70000 h sa0 (64k bytes) feffff h fe0000 h 6ffff h 60000 h www.datasheet.in
mb90820b series 18 ds07-13751-2e block diagram x0 r s t ram rom 6 f 2 mc-16lx bus clock control circ u it, monitor circ u it * 1 cr o s cill a tion circ u it * 1 interr u pt controller cmo s i/o port 1, 2, 4, 5, 7 cmo s i/o port 6 cmo s i/o port 0, 1, 3 , 7, 8 rom correction rom mirroring p 8 2/rto0 (u) * 2 p 83 /rto1 (x) * 2 p 8 4/rto2 (v) * 2 p 8 5/rto 3 (y) * 2 p 8 6/rto4 (w) * 2 p 8 7/rto5 (z) * 2 p10/int0/dtti p60/an0 p61/an1 p62/an2 p6 3 /an 3 p64/an4 p65/an5 p66/an6 p67/an7 cpu f 2 mc-16lx core del a yed interr u pt gener a tor avr av cc av ss a/d converter 16 ( 8 /10- b it) re s et circ u it (w a tchdog timer) other pin s 16- b it ppg timer (ch.0) 16- b it inp u t c a pt u re (ch.0 to ch. 3 ) 16- b it free-r u n timer 16- b it o u tp u t (ch.0 to ch.5) comp a re w a veform gener a tor m u lti-f u nction a l timer 4 p76/in0/an14 p77/in1/an15 p 8 0/in2 p 8 1/in 3 p75/frck/an1 3 uart (ch.0) x1 4 16- b it ppg (ch.1) 16- b it relo a d timer (ch.0) p45/ s in0 p44/ s ot0 p4 3 / s ck0 pwc (ch.1) p46/pwi1 p47/pwo1 p 3 7/ppg0 p42/to0 p41/tin0 p40/ppg1 p16/int6 to p11/int1 p51/int7 uart (ch.1) p72/ s in1/an10 p7 3 / s ot1/an11 p74/ s ck1/an12 16- b it ppg (ch.2) p50/ppg2 16- b it relo a d timer (ch.1) p21/to1 p20/tin1 7 p 3 0 to p 3 6 pwc (ch.0) p06/pwi0 * 2 p07/pwo0 * 2 6 p00 to p05 * 2 p17 6 p22 to p27 8 - b it d/a converter p70/da0/an 8 p71/da1/an9 cmo s i/o port 7 v ss 2, v cc 2, md0 to md2, c time- bas e timer dtp/extern a l interr u pt 8 note : p00 to p07, p10 to p17, p20 to p27 and p30 to p37: with build-in resistors that can be used as input pull-up resistors. *1 : mb90f828b *2 : high current drive pin. www.datasheet.in
mb90820b series ds07-13751-2e 19 memory map note: the rom data of bank ff is reflected to the upper address of bank 00, realizing effective use of the c compiler small model. the lower 16-bit is assigned to the same address, enabling reference of the table on the rom without stating ?far?. for example, if an attempt has been made to access 00c000 h , the contents of the rom at ffc000 h are accessed actually. since the rom area of the ff bank exceeds 32 k bytes, the whole area cannot be reflected in the image for the 00 bank. the rom data at ff8000 h to ffffff h looks, therefore, as if it were the image for 008000 h to 00ffff h . thus, it is recommended that the rom data table be stored in the area of ff8000 h to ffffff h . ffffff h 010000 h 000100 h 0000f0 h 000000 h 0000ff h 0000ef h address #1 - 1 h address #1 00ffff h address #2 - 1 h address #2 address #3 address #3 + 1 h rom area rom area* (ff bank image) ram area register peripheral area : internal access memory : access not allowed parts no. address#1 address#2 address#3 mb90822b ff0000 h 008000 h 0010ff h mb90823b fe0000 h 008000 h 0010ff h mb90f822b ff0000 h 008000 h 0010ff h MB90F823B fe0000 h 008000 h 0010ff h mb90f828b fe0000 h 008000 h 0020ff h mb90v820b (fe0000 h ) 008000 h 0040ff h * : in single chip mode, the mirror function is supported. www.datasheet.in
mb90820b series 20 ds07-13751-2e f 2 mc-16lx cpu prog ramming model dedicated registers ah al usp ssp ps pc dpr pcb dtb usb ssb adb 8-bit 16-bit 32-bit : accumulator (a) dual 16-bit register used for storing results of calculation etc. the two 16-bit registers can be combined to be used as a sequence of 32-bit register. : user stack pointer (usp) the 16-bit pointer indicating the user stack address. : system stack pointer (ssp) the 16-bit pointer indicating the system stack address. : processor status (ps) the 16-bit register indicating the system status. : program counter (pc) the 16-bit register indicating storing location of the current instruction code. : direct page register (dpr) the 8-bit register indicating bit 8 through 15 of the operand address in executing of the short direct addressing. : program bank register (pcb) the 8-bit register indicating the program space. : data bank register (dtb) the 8-bit register indicating the data space. : user stack bank register (usb) the 8-bit register indicating the user stack space. : system stack bank register (ssb) the 8-bit register indicating the system stack space. : additional data bank register (adb) the 8-bit register indicating the additional space. www.datasheet.in
mb90820b series ds07-13751-2e 21 general-purpose registers processor status (ps) r7 r6 r5 r4 r3 r2 r1 rw3 rw2 rw1 rw0 16-bit r0 rw7 rw6 rw5 rw4 rl3 rl2 rl1 rl0 000180 h + (rp 10 h ) maximum of 32 banks b it 15 b it 14 b it 1 3b it 12 b it 11 b it 10 b it 9 b it 8b it 7 b it 6 b it 5 b it 4 ilm rp ccr b it 3b it 2 b it 1 b it 0 ilm2 p s ilm1 ilm0 b4 b 3 b2 b1 b0 i s tnzvc 00000000 01xxxxx initi a l v a l u e : un us ed x : undefined www.datasheet.in
mb90820b series 22 ds07-13751-2e i/o map (continued) address abbreviation register byte access word access resource name initial value 000000 h pdr0 port 0 data register r/w r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w r/w port 4 xxxxxxxx b 000005 h pdr5 port 5 data register r/w r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w r/w port 6 xxxxxxxx b 000007 h pdr7 port 7 data register r/w r/w port 7 xxxxxxxx b 000008 h pdr8 port 8 data register r/w r/w port 8 xxxxxxxx b 000009 h to 00000f h prohibited area 000010 h ddr0 port 0 data direction register r/w r/w port 0 00000000 b 000011 h ddr1 port 1 data direction register r/w r/w port 1 00000000 b 000012 h ddr2 port 2 data direction register r/w r/w port 2 00000000 b 000013 h ddr3 port 3 data direction register r/w r/w port 3 00000000 b 000014 h ddr4 port 4 data direction register r/w r/w port 4 00000000 b 000015 h ddr5 port 5 data direction register r/w r/w port 5 xxxxxx00 b 000016 h ddr6 port 6 data direction register r/w r/w port 6 00000000 b 000017 h ddr7 port 7 data direction register r/w r/w port 7 00000000 b 000018 h ddr8 port 8 data direction register r/w r/w port 8 00000000 b 000019 h to 00001f h prohibited area 000020 h smr0 serial mode register ch.0 r/w r/w uart ch.0 00000000 b 000021 h scr0 serial control register ch.0 w, r/w w, r/w 00000100 b 000022 h sidr0 / sodr0 serial input data register ch.0 / serial output data register ch.0 r/w r/w xxxxxxxx b 000023 h ssr0 serial status register ch.0 r, r/w r, r/w 00001000 b 000024 h smr1 serial mode register ch.1 r/w r/w uart ch.1 00000000 b 000025 h scr1 serial control register ch.1 w, r/w w, r/w 00000100 b 000026 h sidr1 / sodr1 serial input data register ch.1 / serial output data register ch.1 r/w r/w xxxxxxxx b 000027 h ssr1 serial status register ch.1 r, r/w r, r/w 00001000 b www.datasheet.in
mb90820b series ds07-13751-2e 23 (continued) address abbreviation register byte access word access resource name initial value 000028 h pwcsl1 pwc control status register ch.1 r/w r/w pwc timer ch.1 00000000 b 000029 h pwcsh1 r, r/w r, r/w 00000000 b 00002a h pwc1 pwc data buffer register ch.1 ? r/w xxxxxxxx b 00002b h xxxxxxxx b 00002c h div1 divide ratio control register ch.1 r/w r/w xxxxxx00 b 00002d h , 00002e h prohibited area 00002f h pckcr pll clock control register w w pll xxxx0000 b 000030 h enir dtp / interrupt enable register r/w r/w dtp/ external interrupt ch.0 to ch.7 00000000 b 000031 h eirr dtp / interrupt ca use register r/w r/w xxxxxxxx b 000032 h elvrl request level setting register (lower byte) r/w r/w 00000000 b 000033 h elvrh request level setting register (higher byte) r/w r/w 00000000 b 000034 h prohibited area 000035 h cdcr0 clock division ratio control register ch.0 r/w r/w communication prescaler ch.0 00xxx000 b 000036 h prohibited area 000037 h cdcr1 clock division ratio control register ch.1 r/w r/w communication prescaler ch.1 00xxx000 b 000038 h pdcr0 ppg down counter register ch.0 ? r 16-bit ppg timer ch.0 11111111 b 000039 h 11111111 b 00003a h pcsr0 ppg cycle setting register ch.0 ? w xxxxxxxx b 00003b h xxxxxxxx b 00003c h pdut0 ppg duty setting register ch.0 ? w xxxxxxxx b 00003d h xxxxxxxx b 00003e h pcntl0 ppg control status register ch.0 r/w r/w xx000000 b 00003f h pcnth0 r/w r/w 00000000 b 000040 h pdcr1 ppg down counter register ch.1 ? r 16-bit ppg timer ch.1 11111111 b 000041 h 11111111 b 000042 h pcsr1 ppg cycle setting register ch.1 ? w xxxxxxxx b 000043 h xxxxxxxx b 000044 h pdut1 ppg duty setting register ch.1 ? w xxxxxxxx b 000045 h xxxxxxxx b 000046 h pcntl1 ppg control status register ch.1 r/w r/w xx000000 b 000047 h pcnth1 r/w r/w 00000000 b www.datasheet.in
mb90820b series 24 ds07-13751-2e (continued) address abbreviation register byte access word access resource name initial value 000048 h pdcr2 ppg down counter register ch.2 ? r 16-bit ppg timer ch.2 11111111 b 000049 h 11111111 b 00004a h pcsr2 ppg cycle sett ing register ch.2 ? w xxxxxxxx b 00004b h xxxxxxxx b 00004c h pdut2 ppg duty setting register ch.2 ? w xxxxxxxx b 00004d h xxxxxxxx b 00004e h pcntl2 ppg control status register ch.2 r/w r/w xx000000 b 00004f h pcnth2 r/w r/w 00000000 b 000050 h tmrr0 16-bit timer register ch.0 ? r/w waveform generator xxxxxxxx b 000051 h xxxxxxxx b 000052 h tmrr1 16-bit timer register ch.1 ? r/w xxxxxxxx b 000053 h xxxxxxxx b 000054 h tmrr2 16-bit timer register ch.2 ? r/w xxxxxxxx b 000055 h xxxxxxxx b 000056 h dtcr0 16-bit timer control register ch.0 r/w r/w 00000000 b 000057 h dtcr1 16-bit timer control register ch.1 r/w r/w 00000000 b 000058 h dtcr2 16-bit timer control register ch.2 r/w r/w 00000000 b 000059 h sigcr waveform control register r/w r/w 00000000 b 00005a h cpclrb / cpclr compare clear buffer register/ compare clear register ? r/w 16-bit free-run timer 11111111 b 00005b h 11111111 b 00005c h tcdt timer data register ? r/w 00000000 b 00005d h 00000000 b 00005e h tccsl timer control status register (lower) r/w r/w x0100000 b 00005f h tccsh timer control status register (upper) r/w r/w 00000000 b 000060 h ipcp0 input capture data register ch.0 ? r 16-bit input capture (ch.0 to ch.3) xxxxxxxx b 000061 h xxxxxxxx b 000062 h ipcp1 input capture data register ch.1 ? r xxxxxxxx b 000063 h xxxxxxxx b 000064 h ipcp2 input capture data register ch.2 ? r xxxxxxxx b 000065 h xxxxxxxx b 000066 h ipcp3 input capture data register ch.3 ? r xxxxxxxx b 000067 h xxxxxxxx b www.datasheet.in
mb90820b series ds07-13751-2e 25 (continued) address abbreviation register byte access word access resource name initial value 000068 h picsl01 input capture control status register ch.0,ch.1 (lower) r/w r/w 16-bit input capture (ch.0 to ch.3) 00000000 b 000069 h picsh01 ppg output control / input capture control status register ch.0,ch.1 (upper) r, r/w r, r/w 00000000 b 00006a h icsl23 input capture control status register ch.2,ch.3 (lower) r/w r/w 00000000 b 00006b h icsh23 input capture control status register ch.2,ch.3 (upper) r r xxxxxx00 b 00006c h to 00006e h prohibited area 00006f h romm rom mirroring function selection register ww rom mirroring function xxxxxxx1 b 000070 h occpb0 / occp0 output compare buffer register / output compare register ch.0 ? r/w output compare (ch.0 to ch.5) xxxxxxxx b 000071 h xxxxxxxx b 000072 h occpb1 / occp1 output compare buffer register / output compare register ch.1 ? r/w xxxxxxxx b 000073 h xxxxxxxx b 000074 h occpb2 / occp2 output compare buffer register / output compare register ch.2 ? r/w xxxxxxxx b 000075 h xxxxxxxx b 000076 h occpb3 / occp3 output compare buffer register / output compare register ch.3 ? r/w xxxxxxxx b 000077 h xxxxxxxx b 000078 h occpb4 / occp4 output compare buffer register / output compare register ch.4 ? r/w xxxxxxxx b 000079 h xxxxxxxx b 00007a h occpb5 / occp5 output compare buffer register / output compare register ch.5 ? r/w xxxxxxxx b 00007b h xxxxxxxx b 00007c h ocs0 compare control register ch.0 r/w r/w 000 011 00 b 00007d h ocs1 compare control register ch.1 r/w r/w x1 100 000 b 00007e h ocs2 compare control register ch.2 r/w r/w 000 011 00 b 00007f h ocs3 compare control register ch.3 r/w r/w x1 100 000 b 000080 h ocs4 compare control register ch.4 r/w r/w 000 011 00 b 000081 h ocs5 compare control register ch.5 r/w r/w x1 100 000 b 000082 h tmcsrl0 timer control status register ch.0 (lower) r/w r/w 16-bit reload timer (ch.0) 00000000 b 000083 h tmcsrh0 timer control status register ch.0 (upper) r/w r/w xxx10000 b 000084 h tmr0 / tmrd0 16 bit timer register ch.0 / 16-bit reload register ch.0 ? r/w xxxxxxxx b 000085 h xxxxxxxx b 000086 h tmcsrl1 timer control status register ch.1 (lower) r/w r/w 16-bit reload timer (ch.1) 00000000 b www.datasheet.in
mb90820b series 26 ds07-13751-2e (continued) address abbrevia- tion register byte access word access resource name initial value 000087 h tmcsrh1 timer control status register ch.1 (upper) r/w r/w 16-bit reload timer (ch.1) xxx10000 b 000088 h tmr1 / tmrd1 16 bit timer register ch.1 / 16-bit reload register ch.1 ? r/w xxxxxxxx b 000089 h xxxxxxxx b 00008a h csvcr clock supervisor control register* r, r/w ? clock supervisor 00011100 b 00008b h prohibited area 00008c h rdr0 port 0 pull-up resistor setting register r/w r/w port 0 00000000 b 00008d h rdr1 port 1 pull-up resistor setting register r/w r/w port 1 00000000 b 00008e h rdr2 port 2 pull-up resistor setting register r/w r/w port 2 00000000 b 00008f h rdr3 port 3 pull-up resistor setting register r/w r/w port 3 00000000 b 000090 h to 00009d h prohibited area 00009e h pacsr program address detection control status register r/w r/w address match detection xxxx0000 b 00009f h dirr delayed interrupt cause / clear register r/w r/w delayed interrupt xxxxxxx0 b 0000a0 h lpmcr low-power consumption mode control register w, r/w w, r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r, r/w r, r/w 111 111 00 b 0000a2 h to 0000a7 h prohibited area 0000a8 h wdtc watchdog timer control register r, w r, w watchdog timer xxxxx111 b 0000a9 h tbtc time-base timer control register w, r/w w, r/w time-base timer 1xx00100 b 0000aa h to 0000ad h prohibited area 0000ae h fmcs flash memory control status register r, r/w r, r/w flash memory interface circuit 000x0000 b 0000af h prohibited area www.datasheet.in
mb90820b series ds07-13751-2e 27 (continued) address abbreviation register byte access word access resource name initial value 0000b0 h icr00 interrupt control register 00 r/w r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w r/w 00000111 b 0000b2 h icr02 interrupt control register 02 r/w r/w 00000111 b 0000b3 h icr03 interrupt control register 03 r/w r/w 00000111 b 0000b4 h icr04 interrupt control register 04 r/w r/w 00000111 b 0000b5 h icr05 interrupt control register 05 r/w r/w 00000111 b 0000b6 h icr06 interrupt control register 06 r/w r/w interrupt controller 00000111 b 0000b7 h icr07 interrupt control register 07 r/w r/w 00000111 b 0000b8 h icr08 interrupt control register 08 r/w r/w 00000111 b 0000b9 h icr09 interrupt control register 09 r/w r/w 00000111 b 0000ba h icr10 interrupt control register 10 r/w r/w 00000111 b 0000bb h icr11 interrupt control register 11 r/w r/w 00000111 b 0000bc h icr12 interrupt control register 12 r/w r/w 00000111 b 0000bd h icr13 interrupt control register 13 r/w r/w 00000111 b 0000be h icr14 interrupt control register 14 r/w r/w 00000111 b 0000bf h icr15 interrupt control register 15 r/w r/w 00000111 b 0000c0 h pwcsl0 pwc control status register ch.0 r/w r/w pwc timer (ch.0) 00000000 b 0000c1 h pwcsh0 r, r/w r, r/w 00000000 b 0000c2 h pwc0 pwc data buffer register ch.0 ? r/w xxxxxxxx b 0000c3 h xxxxxxxx b 0000c4 h div0 divide ratio control register ch.0 r/w r/w xxxxxx00 b 0000c5 h ader0 a/d input enable register 0 r/w r/w port 6, a/d 11111111 b 0000c6 h adcs0 a/d control status register 0 r/w r/w 8/10-bit a/d converter 000xxxx0 b 0000c7 h adcs1 a/d control status register 1 w, r/w w, r/w 00 000 00x b 0000c8 h adcr0 a/d data register 0 r r xxxxxxxx b 0000c9 h adcr1 a/d data register 1 r r xxxxxxxx b 0000ca h adsr0 a/d setting register 0 r/w r/w 00000000 b 0000cb h adsr1 a/d setting register 1 r/w r/w 00000000 b 0000cc h dat0 d/a data register 0 r/w r/w 8-bit d/a converter xxxxxxxx b 0000cd h dat1 d/a data register 1 r/w r/w xxxxxxxx b 0000ce h dacr0 d/a control register 0 r/w r/w xxxxxxx0 b 0000cf h dacr1 d/a control register 1 r/w r/w xxxxxxx0 b 0000d0 h ader1 a/d input enable register 1 r/w r/w port 7, a/d 11111111 b 0000d1 h to 0000ef h prohibited area www.datasheet.in
mb90820b series 28 ds07-13751-2e (continued) * : for mb90f828b only. prohibited for the other products. meaning of abbreviations used for reading and writing r/w: read and write enabled r: read-only w : write-only explanation of initial values 0 : the bit is initialized to ?0?. 1 : the bit is initialized to ?1?. x : the initial value of the bit is undefined. address abbrevia- tion register byte access word access resource name initial value 0000f0 h to 0000ff h external area 001ff0 h padrl0 program address detection register 0 (lower) r/w r/w address match detection xxxxxxxx b 001ff1 h padrm0 program address detection register 0 (middle) r/w r/w xxxxxxxx b 001ff2 h padrh0 program address detection register 0 (higher) r/w r/w address match detection xxxxxxxx b 001ff3 h padrl1 program address detection register 1 (lower) r/w r/w xxxxxxxx b 001ff4 h padrm1 program address detection register 1 (middle) r/w r/w xxxxxxxx b 001ff5 h padrh1 program address detection register 1 (higher) r/w r/w xxxxxxxx b www.datasheet.in
mb90820b series ds07-13751-2e 29 interrupt factors, interrupt vect ors, interrupt control register : can be used and support the ei 2 os stop request. : can be used and interrupt request flag is cleared by ei 2 os interrupt clear signal. : cannot be used. : usable when an interrupt cause that shares the icr is not used. interrupt cause ei 2 os support interrupt vector interrupt control register priority number address icr address reset #08 08 h ffffdc h ?? high low int9 instruction #09 09 h ffffd8 h ?? exception processing #10 0a h ffffd4 h ?? a/d converter conversion complete #11 0b h ffffd0 h icr00 0000b0 h output compare ch.0 match #12 0c h ffffcc h end of measurement by pwc timer ch.0 / pwc timer ch.0 overflow #13 0d h ffffc8 h icr01 0000b1 h 16-bit ppg timer ch.0 #14 0e h ffffc4 h output compare ch.1 match #15 0f h ffffc0 h icr02 0000b2 h 16-bit ppg timer ch.1 #16 10 h ffffbc h output compare ch.2 match #17 11 h ffffb8 h icr03 0000b3 h 16-bit reload timer ch.1 underflow #18 12 h ffffb4 h output compare ch.3 match #19 13 h ffffb0 h icr04 0000b4 h dtp/ext. interrupt ch.0/ch.1 detection #20 14 h ffffac h dtti output compare ch.4 match #21 15 h ffffa8 h icr05 0000b5 h dtp/ext. interrupt ch.2/ch.3 detection #22 16 h ffffa4 h output compare ch.5 match #23 17 h ffffa0 h icr06 0000b6 h end of measurement by pwc timer ch.1 / pwc timer ch.1 overflow #24 18 h ffff9c h dtp/ext. interrupt ch.4 detection #25 19 h ffff98 h icr07 0000b7 h dtp/ext. interrupt ch.5 detection #26 1a h ffff94 h dtp/ext. interrupt ch.6 detection #27 1b h ffff90 h icr08 0000b8 h dtp/ext. interrupt ch.7 detection #28 1c h ffff8c h waveform generator 16-bit timers ch.0/ ch.1/ch.2 underflow #29 1d h ffff88 h icr09 0000b9 h 16-bit reload timer ch.0 underflow #30 1e h ffff84 h 16-bit free-run timer zero detect #31 1f h ffff80 h icr10 0000ba h 16-bit ppg timer ch.2 #32 20 h ffff7c h input capture ch.0/ch.1 #33 21 h ffff78 h icr11 0000bb h 16-bit free-run timer compare clear #34 22 h ffff74 h input capture ch.2/ch.3 #35 23 h ffff70 h icr12 0000bc h time-base timer #36 24 h ffff6c h uart ch.1 receive #37 25 h ffff68 h icr13 0000bd h uart ch.1 send #38 26 h ffff64 h uart ch.0 receive #39 27 h ffff60 h icr14 0000be h uart ch.0 send #40 28 h ffff5c h flash memory status #41 29 h ffff58 h icr15 0000bf h delayed interrupt generator module #42 2a h ffff54 h www.datasheet.in
mb90820b series 30 ds07-13751-2e electrical characteristics 1. absolute maximum ratings *1 : this parameter is based on v ss = av ss = 0.0 v. *2 : av cc must never exceed v cc when the power is turned on. *3 : v i and v o must never exceed v cc + 0.3 v. however if the maximum curren t to/from an input is limited by some means with external components, the i clamp rating supersedes the v i rating. *4 : the maximum output current is a peak value for a corresponding pin. (continued) parameter symbol rating unit remarks min max power supply voltage* 1 v cc v ss ? 0.3 v ss + 6.0 v av cc v ss ? 0.3 v ss + 6.0 v v cc = av cc * 2 avr v ss ? 0.3 v ss + 6.0 v av cc avr, avr av ss input voltage* 1 v i v ss ? 0.3 v ss + 6.0 v *3 output voltage* 1 v o v ss ? 0.3 v ss + 6.0 v *3 maximum clamp current i clamp ? 2.0 + 2.0 ma *5 total maximum clamp current | i clamp | ? 20 ma *5 ?l? level maximum output current i ol ? 15 ma *4 ?l? level average output current i olav1 ? 4 ma except for p00 to p07, p82 to p87 i olav2 ? 12 ma p00 to p07, p82 to p87 ?l? level total maximum output current i ol ? 100 ma ?l? level total average output current i olav ? 50 ma ?h? level maximum output current i oh ?? 15 ma *4 ?h? level average output current i ohav ?? 4ma ?h? level total maximum output current i oh ?? 100 ma ?h? level total average output current i ohav ?? 50 ma power consumption p d ? 430 mw operating temperature t a ? 40 + 85 c storage temperature tstg ? 55 + 150 c www.datasheet.in
mb90820b series ds07-13751-2e 31 (continued) *5 : ? applicable to pins: p00 to p07, p10 to p17, p20 to p27, p30 to p37, p40 to p47, p50, p51, p80 to p87. ? use within recommended operating conditions. ? use at dc voltage (current). ? the +b signal is an input signal exceeding v cc voltage. the +b signal should always be applied a limiting resistance placed between the +b signal and the microcontroller. ? the value of the limiting resistance should be set so that when the +b signal is applied the input current to the microcontroller pin does not exceed rated values, either instantaneously or for prolonged periods. ? note that when the microcontroller drive current is low, such as in the power saving modes, the +b input potential may pass through the protective diode and increase the potential at the vcc pin, and this may affect other devices. ? note that if a +b signal is input when the microcontr oller power supply is off (not fixed at 0 v), the power supply is provided from the pins, so that incomplete operation may result. ? note that if the +b input is applied during power-on, the power supply is provided from the pins and the resulting supply voltage may not be sufficient to operate the power-on reset. ? care must be taken not to leave the +b input pin open. ? note that analog system input/output pins (lcd drive pins and comparator input pins, etc.) other than the a/d input pins cannot accept +b input. ? sample recommended circuits: warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. input/output equivalent circuits +b input (0 v to 16 v) limiting resistance protective diode vcc p-ch n-ch r www.datasheet.in
mb90820b series 32 ds07-13751-2e 2. recommended operating conditions (v ss = av ss = 0.0 v) *1 : uart ch.0/ch.1 data input pins p45/sin0, p72/sin1/an10 can be used as cmos input by the communication prescaler control register (cdrr). *2 : use a ceramic capacitor or a capacitor with equivalent frequency characteristics. on the v cc pin, connect a bypass capacitor that has a larger capacity than that of c s . refer to the following figure for connection of smoothing capacitor c s . (continued) parameter sym- bol pin name condi- tion value unit remarks min max power supply voltage v cc av cc ?? 4.5 5.5 v at normal operation t a = ? 40 c to + 85 c ?? 4.0 5.5 v normal operation when d/a converter is not used t a = ? 40 c to + 85 c ?? 3.5 5.5 v normal operation when a/d converter and d/a converter are not used t a = ? 40 c to + 85 c ?? 3.0 5.5 v maintains state in stop mode ?h? level input voltage v ih p30 to p37, p60 to p67 v cc = 5 v 10 % 0.7 v cc v cc + 0.3 v cmos input v ihs p00 to p07, p10 to p17, p20 to p27, p40 to p44, p45* 1 , p46, p47, p50, p51, p70, p71, p72* 1 , p73 to p77, p80 to p87, rst 0.8 v cc v cc + 0.3 v cmos hysteresis input v ihm md0, md1, md2 v cc ? 0.3 v cc + 0.3 v md input ?l? level input voltage v il p30 to p37, p60 to p67 v ss ? 0.3 0.3 v cc vcmos input v ils p00 to p07, p10 to p17, p20 to p27, p40 to p44, p45* 1 , p46, p47, p50, p51, p70, p71, p72* 1 , p73 to p77, p80 to p87, rst v ss ? 0.3 0.2 v cc v cmos hysteresis input v ilm md0, md1, md2 v ss ? 0.3 v ss + 0.3 v md input smoothing capacitor c s ?? 0.1 1.0 f*2 reference input voltage of a/d converter avr ?? 2.7 av cc v operating temperature t a ??? 40 + 85 c www.datasheet.in
mb90820b series ds07-13751-2e 33 (continued) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the device's el ectrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within thei r recommended operating condition ranges. operation outside these ranges ma y adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operat ing conditions, or combinations not represented on the data sheet. users considering application outsi de the listed conditions are advised to contact their representatives beforehand. c pin connection circuit c c s www.datasheet.in
mb90820b series 34 ds07-13751-2e 3. dc characteristics (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (continued) parameter symbol pin name condition value unit remarks min typ max ?h? level output voltage v oh all output pins v cc = 4.5 v, i oh = ? 4.0 ma v cc ? 0.5 ?? v ?l? level output voltage v ol1 all pins except p00 to p07 p82 to p87 v cc = 4.5 v, i ol1 = 4.0 ma ?? 0.4 v v ol2 p00 to p07 p82 to p87 v cc = 4.5 v, i ol2 = 12.0 ma ?? 0.4 v input leakage current i il all input pins v cc = 5.5 v, v ss < v i < v cc ? 5 ? + 5 a at pull-up disabled pull-up resistance r up p00 to p07, p10 to p17, p20 to p27, p30 to p37, rst ? 25 50 100 k ? mask rom product pull-down resistance r down md2 ? 25 50 100 k ? mask rom product www.datasheet.in
mb90820b series ds07-13751-2e 35 (continued) (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : the power supply current is regulated with an external clock. parameter symbol pin name condition value unit remarks min typ max power supply current* i cc v cc v cc = 5.0 v, internal frequency: 24 mhz, at normal operation ? 35 50 ma mask rom product ? 45 60 ma flash memory prod- uct v cc = 5.0 v, internal frequency: 24 mhz, at writing in flash memory ? 60 75 ma flash memory prod- uct v cc = 5.0 v, internal frequency: 24 mhz, at erasing memory ? 65 80 ma flash memory prod- uct i ccs v cc = 5.0 v, internal frequency: 24 mhz, at sleep mode ? 15 25 ma mask rom product ? ma flash memory prod- uct i cts v cc = 5.0 v, internal frequency: 2 mhz, at main timer mode ? 0.3 0.8 ma mask rom product ? ma flash memory prod- uct i cct v cc = 5.0 v, internal frequency: 8 mhz, at timer mode, t a = + 25 c ? 37 ma mask rom product ? ma flash memory prod- uct i cch in stop mode, t a = + 25 c ? 520 a mask rom product ? ma flash memory prod- uct input capacitance c in except av cc , av ss , avr, c, v cc and v ss ?? 515pf www.datasheet.in
mb90820b series 36 ds07-13751-2e 4. ac characteristics (1) clock timings (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name value unit remarks min typ max clock frequency f c x0, x1 3 ? 16 mhz when using oscillation circuit 3 ? 24 when using external clock 4 ? 24 1 multiplied pll 4 ? 12 2 multiplied pll 4 ? 8 3 multiplied pll 4 ? 6 4 multiplied pll 4 ? 4 6 multiplied pll clock cycle time t hcyl x0, x1 62.5 ? 333 ns when using oscillation circuit 41.67 ? 333 ns when using external clock input clock pulse width p wh , p wl x0 10 ?? ns when using external clock, duty ratio is about 30% to 70%. input clock rise/fall time t cr t cf x0 ?? 5ns when using external clock internal operating clock frequency f cp ? 1.5 ? 24 mhz internal operating clock cycle time t cp ? 41.67 ? 666 ns x0 t hcyl t cf t cr 0.8 v cc 0.2 v cc p wh p wl www.datasheet.in
mb90820b series ds07-13751-2e 37 the ac ratings are measured for the following measurement reference voltages operation guarantee range of pll power supply voltage v cc (v) normal operation guarantee range internal operating clock frequency f cp (mhz) relationship between internal operating clock frequency and power supply voltage relationship between clock frequency and internal operating clock frequency clock frequency f c (mhz) internal operating clock frequency f cp (mhz) not multiplied x4 24 4 1.5 5.5 3.5 4 12 16 24 34 8 16 1.5 8 4.5 4.0 12 guaranteed d/a converter operating range guaranteed a/d converter operating range 24 x6 x3 x2 x1 0.8 v cc 0.2 v cc 2.4 v 0.8 v 0.7 v cc 0.3 v cc input signal waveform hysteresis input pin pins other than hysteresis input/md input output signal waveform output pin www.datasheet.in
mb90820b series 38 ds07-13751-2e (2) external reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : oscillation time of oscillator is the time to reach to 90% of the oscillation am plitude from stand still. in the crystal oscillator, the oscillation time is between several ms to tens of ms. in cerami c oscillator, the oscillation time is between hundreds of s to several ms. in the external clock, the oscillation time is 0 ms. parameter symbol pin name value unit remarks min max reset input time t rstl rst 500 ? ns in normal operation oscillation time of oscillator* + 100 ? s in stop mode 100 ? s in time-base timer mode ? in normal operation mode ? in stop mode, at power on rst 0.2 v cc t rstl 0.2 v cc t rstl 0.2 v cc 0.2 v cc rst x0 internal operation clock oscillation time of oscillator 90 % of the oscillation amplitude 100 s oscillator stabilization time instruction execution internal reset www.datasheet.in
mb90820b series ds07-13751-2e 39 (3) power-on reset (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) note : sudden changes in the power supply voltage may cause a power-on reset. to change the power supply voltage while the device is in operation, be sure to set the slope of rising within 50 mv/ms or less as shown below. parameter symbol pin name condition value unit remarks min max power supply rising time t r v cc ? 0.05 30 ms power supply cut-off time t off v cc 1 ? ms waiting time for power supply on v cc t r t off 2.7 v 0.2 v 0.2 v 0.2 v v cc v ss 3.0 v be sure to set the slope of rising within 50 mv/ms or less. ram data hold time www.datasheet.in
mb90820b series 40 ds07-13751-2e (4) uart (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) notes : ? these are ac ratings in the clk synchronous mode. ? cl is the load capacitance value connected to pins while testing. ? t cp is machine cycle time (unit : ns). parameter symbol pin name condition value unit min max serial clock cycle time t scyc sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of internal shift clock mode 8 t cp ? ns sck sot delay time t slov sck0 to sck1 sot0 to sot1 ? 80 + 80 ns valid sin sck t ivsh sck0 to sck1 sin0 to sin1 100 ? ns sck valid sin hold time t shix sck0 to sck1 sin0 to sin1 60 ? ns serial clock ?h? pulse width t shsl sck0 to sck1 c l = 80 pf + 1 ttl for an output pin of ex- ternal shift clock mode 4 t cp ? ns serial clock ?l? pulse width t slsh sck0 to sck1 4 t cp ? ns sck sot delay time t slov sck0 to sck1 sot0 to sot1 ? 150 ns valid sin sck t ivsh sck0 to sck1 sin0 to sin1 60 ? ns sck valid sin hold time t shix sck0 to sck1 sin0 to sin1 60 ? ns www.datasheet.in
mb90820b series ds07-13751-2e 41 sck sot sin sck sot sin t scyc t slov t ivsh t shix 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc t slsh t shsl t slov t ivsh t shix 0.2 v cc 0.2 v cc 0.8 v cc 0.8 v cc 2.4 v 0.8 v 0.8 v cc 0.2 v cc 0.8 v cc 0.2 v cc internal shift clock mode external shift clock mode www.datasheet.in
mb90820b series 42 ds07-13751-2e (5) resources input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) (6) trigger input timing (v cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) parameter symbol pin name condition value unit min max input pulse width t tiwh t tiwl in0 to in3, tin0 to tin1, pwi0 to pwi1, dtti ? 4 t cp ? ns parameter symbol pin name condition value unit min max input pulse width t trgh t trgl int0 to int7 ? 5 t cp ? ns 0.8 v cc in0 to in3, tin0 to tin1, pwi0 to pwi1, dtti 0.8 v cc 0.2 v cc 0.2 v cc t tiwh t tiwl 0.8 v cc int0 to int7 0.8 v cc 0.2 v cc 0.2 v cc t trgh t trgl www.datasheet.in
mb90820b series ds07-13751-2e 43 5. a/d converter electrical characteristics (3.0 v avr ? av ss , v cc = av cc = 5.0 v 10 % , v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : the current when the a/d converter is not operating or the cpu is in stop mode (for v cc = av cc = avr = 5.0 v) note : the error increases proportionally as |avr - av ss | decreases. parameter symbol pin name condi- tion value unit remarks min typ max resolution ?? ? ? 10 ? bit total error ?? ? ? 3.0 lsb non-linearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition voltage v ot an0 to an15 av ss ? 1.5 lsb av ss + 0.5 lsb av ss + 2.5 lsb v full-scale transition voltage v fst an0 to an15 avr ? 3.5 lsb avr ? 1.5 lsb avr + 0.5 lsb v compare time ?? 1.0 ?? s 4.5 v < avcc < 5.5 v 2.0 ?? s 4.0 v < avcc < 4.5 v sampling time ?? 0.5 ?? s 4.5 v < avcc < 5.5 v 1.2 ?? s 4.0 v < avcc < 4.5 v analog port input current i ain an0 to an15 ? 0.3 ? + 0.3 a analog input voltage v ain an0 to an15 av ss ? avr v reference voltage ? avr av ss + 2.7 ? av cc v power supply current i a av cc ? 2.4 4.7 ma i ah ?? 5 a* reference voltage supply current i r avr ? 600 900 a i rh ?? 5 a* offset between channels ? an0 to an15 ?? 4lsb www.datasheet.in
mb90820b series 44 ds07-13751-2e 6. a/d converter glossary resolution : analog variation that is recognized by an a/d converter. non linearity error : deviation between a line across zero-transition line (?00 0000 0000? ? ?00 0000 0001?) and full-scale transition line (?11 1111 1110? ? ?11 1111 1111?) and actual conversion characteristics. differential linearity error : deviation of input voltage, which is required for changing output code by 1 lsb, from an ideal value total error : difference between an actual value and an ideal value. a total error includes zero transition error, full-scale transition error, and linear error. (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h av ss avr v nt {1 lsb (n ? 1) + 0.5 lsb} 1.5 lsb 0.5 lsb total error actual conversion characteristics analog input total error for digital output n = v nt ? {1 lsb (n ? 1) + 0.5 lsb} 1 lsb [lsb] 1 lsb = (ideal value) avr ? avss 1024 [v] v ot (ideal value) = avss + 0.5 lsb [v] v fst (ideal value) = avr ? 1.5 lsb [v] v nt : voltage at which of digital output transitions from (n ? 1) h to n h . actual conversion characteristics ideal characteristics (measurement value) digital output n : a/d converter digital output value www.datasheet.in
mb90820b series ds07-13751-2e 45 (continued) 3ff h 3fe h 3fd h 004 h 003 h 002 h 001 h avss avr avss avr (n + 1) h n h (n ? 1) h (n ? 2) h v nt v nt v (n + 1)t v ot v fst {1 lsb (n ? 1) + v ot } linearity error ideal characteristics (measurement value) digital output differential linearity error (measurement value) (measurement value) linearity error of digital output n v nt ? {1 lsb (n ? 1) + v ot } 1 lsb [lsb] = differential linearity error of digital output n v ( n + 1 ) t ? v nt 1 lsb ? 1 [lsb] = v fst ? v ot 1022 [v] 1 lsb = v ot : voltage at which of digital output transmissions from ?000 h ? to ?001 h ?. v fst : voltage at which of digital output transmissions from ?3fe h ? to ?3ff h ?. actual conversion characteristics actual conversion characteristics actual conversion characteristics actual conversion characteristics ideal characteristics (measurement value) (measurement value) digital output analog input analog input n : a/d converter digital output value www.datasheet.in
mb90820b series 46 ds07-13751-2e 7. notes on using a/d converter ? about the external impedance of the analog input and its sampling time a/d converter with sample and hold circuit. if the external impedance is too high to keep sufficient sampling time, the analog voltage charged to the internal sample and hold capacitor is insufficient, adversely affecting a/d conversion precision. therefore, to satisfy the a/d conversion precision standard, consider the relationship between the external impedance and minimum sampling time and either adjust the resistor value and operating frequency or decrease the external impedance so that the sampling time is longer than the minimum value. and if the sampling time cannot be sufficient, connect a capacitor of about 0.1 f to the analog input pin. about the error the accuracy gets worse as | avr ? av ss | becomes smaller. r c rc mb90822b/823b 2.0 k ? (max) 14.4 pf (max) mb90f822b/f823b 2.0 k ? (max) 16.0 pf (max) ? analog input circuit model analog input during sampling : on comparator note : the values are reference values. mb90f822b/f823b mb90822b/ 823b 0 5 10 15 20 25 30 35 0 10 20 30 40 50 60 70 80 90 100 mb90f822b/f823b mb90822b/ 823b 012345678 0 2 4 6 8 10 12 14 16 18 20 (external impedance = 0 k ? to 100 k ? ) (external impedance = 0 k ? to 20 k ? ) external impedance [k ? ] minimum sampling time [ s] external impedance [k ? ] minimum sampling time [ s] ? the relationship between the external impedance and minimum sampling time www.datasheet.in
mb90820b series ds07-13751-2e 47 8. electrical characteristics of d/a convertor (v cc = av cc = 4.5 v to 5.5 v, v ss = av ss = 0.0 v, t a = ? 40 c to + 85 c) * : with load capacitance 20 pf. parameter symbol pin name condition value unit remarks min typ max resolution ?? ? ? 8 ? bit differential linearity error ?? ?? 0.5 lsb conversion time ?? ? 0.45 ? s* analog output impedance ?? ? 2.9 3.8 k ? power supply current i dvr av cc ? 160 920 a i dvrs ? 0.1 ? a d/a stops www.datasheet.in
mb90820b series 48 ds07-13751-2e 9. flash memory program/erase characteristics * : this value comes from the technology qualification (using arrhenius equation to translate high temperature measurements into normalized value at + 85 c) . ordering information parameter condition value unit remarks min typ max sector erase time t a = +25 c v cc = 5.0 v ? 115s excludes programming prior to erasure chip erase time ? 9 ? s excludes programming prior to erasure word (16 bit width) programing time ? 16 3,600 s except for the overhead time of the system program/erase cycle ? 10,000 ?? cycle flash data retention time average t a = +85 c 20 ?? year * part number package MB90F823Bpmc mb90f822bpmc mb90822bpmc mb90823bpmc mb90f828bpmc 80-pin plastic lqfp (fpt-80p-m21) MB90F823Bpmc1 mb90f822bpmc1 mb90822bpmc1 mb90823bpmc1 mb90f828bpmc1 80-pin plastic lqfp (fpt-80p-m22) MB90F823Bpf mb90f822bpf mb90822bpf mb90823bpf mb90f828bpf 80-pin plastic qfp (fpt-80p-m06) www.datasheet.in
mb90820b series ds07-13751-2e 49 package dimensions please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 8 0-pin pl as tic lqfp le a d pitch 0.50 mm p a ck a ge width p a ck a ge length 12 mm 12 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.47 g code (reference) p-lfqfp 8 0-12 12-0.50 8 0-pin pl as tic lqfp (fpt- 8 0p-m21) (fpt- 8 0p-m21) c 2006 fujit s u limited f 8 00 3 5 s -c-2-2 120 40 21 60 41 8 0 61 index 12.000.10(.472.004) s q 14.000.20(.551.00 8 ) s q 0.50(.020) 0.200.05 (.00 8 .002) m 0.0 8 (.00 3 ) 0.1450.055 (.006.002) 0.0 8 (.00 3 ) "a" 0 ? ~ 8 ? .059 ?.004 +.00 8 ?0.10 +0.20 1.50 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0.100.05 (.004.002) ( s t a nd off) 0.25(.010) det a il s of "a" p a rt lead no. (mo u nting height) * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s ?2006-200 8 fujit s u microelectronic s limited f 8 00 3 5 s -c-2- 3 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. www.datasheet.in
mb90820b series 50 ds07-13751-2e please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ (continued) 8 0-pin pl as tic lqfp le a d pitch 0.65 mm p a ck a ge width p a ck a ge length 14.00 mm 14.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 1.70 mm m a x weight 0.62 g code (reference) p-lfqfp 8 0-14 14-0.65 8 0-pin pl as tic lqfp (fpt- 8 0p-m22) (fpt- 8 0p-m22) c 2007 fujit s u limited f 8 00 3 6 s -c-1-1 120 21 40 61 8 0 41 60 14.000.10(.551.004) s q 16.000.20(.6 3 0.00 8 ) s q index 0.65(.026) 0. 3 20.05 (.01 3 .002) m 0.1 3 (.005) "a" (.006.002) 0.1450.055 0.10(.004) 0.500.20 (.020.00 8 ) 0.600.15 (.024.006) 0~ 8 ? .059 ?.004 +.00 8 ?0.10 +0.20 1.50 (mo u nting height) 0.25(.010) 0.100.10 (.004.004) ( s t a nd off) det a il s of "a" p a rt * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . ?2007-200 8 fujit s u microelectronic s limited f 8 00 3 6 s -c-1-2 note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 ) pin s width do not incl u de tie ba r c u tting rem a inder. www.datasheet.in
mb90820b series ds07-13751-2e 51 (continued) please confirm the la test package dimens ion by following url. http://edevice.fujitsu.com/package/en-search/ 8 0-pin pl as tic qfp le a d pitch 0. 8 0 mm p a ck a ge width p a ck a ge length 14.00 20.00 mm le a d s h a pe g u llwing s e a ling method pl as tic mold mo u nting height 3 . 3 5 mm max code (reference) p-qfp 8 0-14 20-0. 8 0 8 0-pin pl as tic qfp (fpt- 8 0p-m06) ( fpt- 8 0p-m06 ) c 2002-200 8 fujit s u microelectronic s limited f 8 0010 s -c-6-6 1 24 25 40 41 64 65 8 0 20.000.20(.7 8 7.00 8 ) 2 3 .900.40(.941.016) 14.000.20 (.551.00 8 ) 17.900.40 (.705.016) index 0. 8 0(.0 3 1) 0. 3 70.05 (.015.002) m 0.16(.006) "a" 0.170.06 (.007.002) 0.10(.004) 0. 8 00.20 (.0 3 1.00 8 ) 0. 88 0.15 (.0 3 5.006) 0~ 8 .120 ?.00 8 +.012 ?0.20 +0. 3 0 3 .05 0.25(.010) 0. 3 0 +0.10 ?0.25 +.004 ?.010 .012 ( s t a nd off) det a il s of "a" p a rt (mo u nting height) * * dimen s ion s in mm (inche s ). note: the v a l u e s in p a renthe s e s a re reference v a l u e s . note 1) * : the s e dimen s ion s do not incl u de re s in protr us ion. note 2) pin s width a nd pin s thickne ss incl u de pl a ting thickne ss . note 3 )pin s width do not incl u de tie ba r c u tting rem a inder. www.datasheet.in
mb90820b series 52 ds07-13751-2e main changes in this edition the vertical lines marked in the left side of the page show the changes. page section change results 4 package and corresponding products changed the mb90822b (fpt-80p-m21). x : not available : available 43 electrical characteristics 5. a/d converter electrical characteristics changed the unit of zero transition voltage and full-scale tran- sition voltage. mv v 48 ordering information added the part number. mb90822bpmc mb90823bpmc www.datasheet.in
mb90820b series ds07-13751-2e 53 memo www.datasheet.in
mb90820b series 54 ds07-13751-2e memo www.datasheet.in
mb90820b series ds07-13751-2e 55 memo www.datasheet.in
mb90820b series fujitsu microelectronics limited shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0722, japan tel: +81-3-5322-3347 fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ for further information please contact: north and south america fujitsu microelectronics america, inc. 1250 e. arques avenue, m/s 333 sunnyvale, ca 94085-5401, u.s.a. tel: +1-408-737-5600 fax: +1-408-737-5999 http://www.fma.fujitsu.com/ europe fujitsu microelectronics europe gmbh pittlerstrasse 47, 63225 langen, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://emea.fujitsu.com/microelectronics/ korea fujitsu microelectronics korea ltd. 206 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ asia pacific fujitsu microelectronics asia pte ltd. 151 lorong chuan, #05-08 new tech park, singapore 556741 tel: +65-6281-0770 fax: +65-6281-0220 http://www.fujitsu.com/sg/services/micro/semiconductor/ fujitsu microelectronics shanghai co., ltd. rm.3102, bund center, no.222 yan an road(e), shanghai 200002, china tel: +86-21-6335-1560 fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ fujitsu microelectronics pacific asia ltd. 10/f., world commerce centre, 11 canton road tsimshatsui, kowloon hong kong tel: +852-2377-0226 fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with sales representative s before ordering. the information, such as descri ptions of function and applicati on circuit examples, in this docum ent are presented solely for t he purpose of reference to show examples of ope rations and uses of fujits u microelectronics device; fujitsu microelectronics does not warrant proper operation of the device with respect to use based on such information. when you develop equipment incor porat- ing the device based on such in formation, you must assume any responsibility arising out of such use of the information. fujitsu microelectronics assumes no liab ility for any damages whatsoever arisi ng out of the use of the information. any information in this document, including descriptions of function and schematic di agrams, shall not be construed as license of the use or exercise of any intellectual property ri ght, such as patent right or copyright, or any other right of fujitsu microelectroni cs or any third party or does fujitsu microel ectronics warrant non-infringeme nt of any third-party's intellectual property right o r other right by using such information. fu jitsu microelectronics assumes no liability for any infringement of the intellectual property rights or other rights of third parties which w ould result from the use of in formation cont ained herein. the products described in this document are designed, developed and manufa ctured as contemplated fo r general use, including wit hout limitation, ordinary indus trial use, general office use, personal use, and household use, but are not designed, developed and m anufactured as contemplated (1) for use acco mpanying fatal risks or dangers th at, unless extremely high safety is secured, could have a ser ious effect to the public, and could lead directly to death, personal injury, severe physical damage or other lo ss (i.e., nuc lear reaction control in nuclear facility, airc raft flight control, air traffic c ontrol, mass transport control, me dical life support system, missile la unch control in weapon system), or (2) for use requiring extremely high re liability (i.e ., submersible repeater and artificial satellite). please note that fujitsu microelectronics will not be liable against you and/or any th ird party for any clai ms or damages arisi ng in connection with above-men tioned uses of the products. any semiconductor devices have an inherent ch ance of failure. you must protect against injury, damage or loss from such failure s by incorporating safety desi gn measures into your facility and equipment such as redundancy, fire protection, and prevention of ov er-current levels and other abnor mal operating conditions. exportation/release of any products described in this docum ent may require necessary procedures in accordance with the regulati ons of the foreign exchange and foreign trade control law of japan and/or us export control laws. the company names and brand na mes herein are the trademarks or registered trademarks of their respective owners. edited business & media promotion dept. www.datasheet.in

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